Fault Models and Tests for a 2-Bit-per-Cell MLDRAM

capacity of monolithic dynamic randomaccess memories (DRAMs) has increased by six orders of magnitude through a combination of design innovations and improvements of existing technology.1,2 Design innovations include the folded bit-line cell array arrangement and compact, high-capacitance, threedimensional cell designs such as the stacked capacitor and trench capacitor cells. Technology improvements include increases in die area and, most importantly, reductions in minimum feature size.1,2 Further increases in DRAM storage density through the use of still smaller feature sizes face serious challenges from increasingly high fabrication facility costs. Monolithic digital systems increasingly employ embedded DRAMs; however, some of the density advantage of DRAMs over static RAMs is lost because conventional logic processes support only planar cell capacitor designs. An often-proposed design innovation for achieving higher storage density without further reductions in feature size or complex 3D cell structures is to hold more than one bit per storage cell. The potential for storing more than two resolvable analog voltages on the capacitance of a storage cell facilitates this idea in DRAMs. In this article, we describe a fault model for a 2-bit-per-cell MLDRAM proposed by Gillingham.3 We derived the fault model using manual analysis and confirmed it with analog SPICE simulation. We modified accurate circuit models obtained from MOSAID Technologies to produce the effects of physical defects similar to those reported for 1-bit-per-cell DRAMs with similar cell array layouts. We also propose an efficient test for the fault model and possible MLDRAM design-for-testability enhancements.